1. Field of the Invention
This invention relates to semiconductor processing and more particularly to a semiconductor gate conductor having an impurity diffusion barrier and method for producing the same.
2. Background of the Relevant Art
Fabrication of a MOS device generally begins with a bulk silicon substrate having one or more wells of opposite dopant polarity placed within the substrate. Source and drain regions are then diffused or implanted into the substrate and well areas such that the source and drain regions are of opposite dopant polarity than the well or substrate. Accordingly, a complementary MOS, or CMOS, device can be formed having both n-channel and p-channel active devices or field effect transistors (FETs).
Very large scale integration (VLSI) processing dictates that active devices be placed close to one another in a dense fashion. As such, source and drain regions are often implanted or diffused at very shallow depths. Moreover, the spacing between the source and drain regions, or channel length, is oftentimes less than a few microns, and in some instances less than one micron. To ensure that the source and drain regions substantially maintain their original shape (i.e., do not continue to out-diffuse deeper or wider than a target amount), it is sometimes imperative that closely spaced devices have a diffusion barrier placed within the source/drain regions. U.S. Pat. No. 4,835,112 (incorporated herein by reference) utilizes a germanium barrier to retard or substantially prevent diffusion of the source/drain regions beyond an initial target amount. Germanium ions are implanted into the source/drain regions along with the n+ or p+ dopants, phosphorous or boron, respectively. As taught in Patent '112, germanium, used as a barrier, retards lateral diffusion and reduces many problems associated therewith, including lessening of hot carrier injection and reducing the amount of shrinkage in the effective channel length (Leff) of the active device.
Implantation of germanium ions into the source/drain region can also help reduce contact resistance between the source/drain material and overlying silicide. See, e.g., U.S. Pat. No. 5,108,954 (incorporated herein by reference). Patent '954 utilizes germanium within the source/drain to retard or substantially prevent diffusion of dopant material from the source/drain to the silicide at the immediate juncture between the silicide and source/drain. Germanium is used to prevent a void caused by diffusivity of conductivity enhancing dopant at the juncture, and to prevent loss of conductivity as a result of that void. Consequently, source/drain regions utilizing a germanium barrier near the silicide can provide and maintain a better ohmic contact between an overlying metallization layer and the source/drain.
While it is important to maintain precise source/drain diffusion geometry and low resistance contact thereto, it is also important that the diffusion impurity chosen not adversely affect the channel region concentration. Specifically, recent studies indicate a problem associated with p-channel MOS (PMOS) FET manufacture, whereby p+ dopant of boron from a boron difluoride (BF.sub.2) carrier will penetrate, diffuse, or migrate through the thin gate oxide from the gate conductor to the underlying channel region. See, e.g., Sung, et al., "Fluorine Effect on Boron Diffusion of P+ Gate Devices," IEDM (1989), pp. 447-450. The channel region must maintain closely controlled n- dopant level generally set by the substrate manufacturer. Generally speaking, a PMOS device is manufactured using a self-aligned process having source and drain regions implanted simultaneous with the gate conductor (such as polycrystalline silicon or "polysilicon"), wherein the gate conductor is configured over the channel region between the source and drain. Not only must the lateral diffusions be minimized and controlled as described above, but also the diffusion of p+impurities through the thin gate oxide via the polysilicon gate must also be minimized and controlled. As defined herein, "conductive material" or "gate conductor" refers to undoped polysilicon which becomes conductive after impurity implant and anneal.
It has been recently discovered that titanium silicide deposited on the upper surface of the gate prior to dopant introduction will substantially block boron difluoride (BF.sub.2) from being implanted into the gate. Absence of boron or BF.sub.2 in the gate will therefore ensure that it will not subsequently enter the channel via the gate during anneal. See, e.g., Baker et al., "The Influence of Fluorine on Threshold Voltage Instabilities in P+ Polysilicon gated P-Channel MOSFETs," IEDM, (1989), pp. 443-446. As described in Baker, et al., boron introduction into the channel region, derived from the boron fluoride, causes a change in the concentration level of the n- channel substrate. Slight change in channel concentration will cause a shift in threshold voltage, Vth, and flatband voltage, Vfb, of the operating device. An alternative solution to preventing boron penetration proposed by Baker et al., is to use elemental boron instead of boron fluoride (BF.sub.2). However, it is well known that fluorine is a beneficial carrier in PMOS diffusion areas and remains a mainstay in PMOS fabrication.
Titanium silicide placed across the upper gate area prior to dopant implantation provides the user with the benefits of BF.sub.2 and appears to solve the BF.sub.2 penetration problem. However, titanium silicide selectively placed across only the gate region prior to source/drain implantation generally requires a separate masking step and associated photolithography. The masking step must eventually be repeated in order to provide a high conductivity silicide over the source/drain contact regions after the source/drain areas are implantated. Requiring two photolithography steps and associated masks can prove problematic and should in most cases be avoided if only one step is needed. Alternatively, titanium silicide can be placed across the entire active area (gate and source/drain regions) prior to a high energy implantation through the silicide. Blanket deposition of titanium silicide in the active regions follows normal processing flow without requiring additional masks or steps. However, blanket deposition and subsequent high energy implantation cannot ensure BF.sub.2 is prevented from entering the gate while permitting accurate (e.g., shallow) implantation into the source/drain.